| |------------------------------------------------------------------------------- | block definition section |------------------------------------------------------------------------------- | [DIE_Block] | block_DIE_format_version 1.0 04/08/94; block_level 0; | block_version 1.0 4/10/94; block_source authors: REH, Logic Modeling Corporation & LFS, Logic Modeling Corporation ; block_disclaimer These models are provided as a demonstration vehicle for the DIE Format version 1.0. LMC does not assume any liability arising out of the application or use of any information described herein. The information is provided purely for example purposes. Any likeness to an actual device is purely coincidental. ; block_notes This block represents an example of DIE format version 1.0; |------------------------------------------------------------------------------- | National Semiconductor SCAN 18245T MDA Bare Die | |------------------------------------------------------------------------------- | pad geometry definition sections |------------------------------------------------------------------------------- | [pad_geom] pad_geom_name 3_8milsquare; pad_geom_shape rectangle 3.8mil 3.8mil; pad_geom_metal_extent 0.0 0.0 rectangle 4.0mil 4.0mil; pad_geom_passivation_extent 0.0 0.0 rectangle 3.8mil 3.8mil; pad_geom_bond_sites 1 0.0mil 0.0mil; | Single bond site at center of pad | pad_geom_tolerance | none given! | [pad_geom] pad_geom_name 3_8milwide; pad_geom_shape rectangle 3.8mil 8.08mil; pad_geom_metal_extent 0.0 0.0 rectangle 4.0mil 8.5mil; pad_geom_passivation_extent 0.0 0.0 rectangle 3.8mil 8.08mil; pad_geom_bond_sites 2 0.0mil 2.18mil 0.0mil -2.18mil; | pad_geom_tolerance | none given! | The National Semi data sheet specifies the | center of two 3.8mil pads separated by | 0.48mil. It actually represents a single pad. | |------------------------------------------------------------------------------- | pad digital signal definition sections |------------------------------------------------------------------------------- | [pad_digital] pad_digital_name cmos_input_pad; pad_digital_circuit cmos input; pad_digital_threshold 4.5V 2.0V 1.0uA 0.8V 1.0uA, 5.5V 2.0V 1.0uA 0.8V 1.0uA; pad_digital_ibis_model s18245t.ibs input1; | [pad_digital] pad_digital_name cmos_test_pad; pad_digital_circuit cmos input; pad_digital_threshold 5.5V 2.0V 3.7uA 0.8V -385.0uA; pad_digital_ibis_model s18245t.ibs input2; | [pad_digital] pad_digital_name cmos_output_pad; pad_digital_circuit cmos output; pad_digital_pull_down 4.5V 48mA 0.55V, 4.5V 50uA 0.1V, 5.5V 53mA 0.55V, 5.5V 50uA 0.1V; pad_digital_pull_up 4.5V -24mA 2.4V, 4.5V -50uA 3.15, 5.5V -27mA 2.4V, 5.5V -50uA 4.15; pad_digital_ibis_model s18245t.ibs output1; | [pad_digital] pad_digital_name cmos_io_pad; pad_digital_circuit cmos input tristate; pad_digital_threshold 5.5V 2.0V 1.0uA 0.8V 1.0uA; pad_digital_pull_down 4.5V 48mA 0.55V, 5.5V 63mA 0.55V; pad_digital_pull_up 4.5V -24mA 2.4V, 5.5V -27mA 2.4V; pad_digital_ibis_model s18245t.ibs transceiver; | |------------------------------------------------------------------------------- | power supply pad definition sections |------------------------------------------------------------------------------- | [pad_supply] pad_supply_name VCC_supply; pad_supply_voltage fixed 5.0V 4.5V 5.5V; pad_supply_current_max 70mA; | [pad_supply] pad_supply_name GND_supply; pad_supply_voltage fixed 0.0V 0.0V 0.0V; pad_supply_current_max 70mA; | |------------------------------------------------------------------------------- | die definition sections |------------------------------------------------------------------------------- | [die] |------------------------------------------------------------------------------- | administration information |------------------------------------------------------------------------------- die_type bare; die_name SCAN18245T-MDA; die_manufacturer National Semiconductor; die_mask_version 0; not found in the data sheet | die_section_version 1.1 29/10/92; die_source Information is taken from National Semiconductor SCAN18245T MDA data sheet September 1993.; | |------------------------------------------------------------------------------- | design information |------------------------------------------------------------------------------- die_technology CMOS; die_description (Known Good Die) Serially Controlled Access Network Non-inverting Transceiver with TRI-STATE Outputs. The SCAN18245T is a high speed, low-power bidirectional line driver featuring separate data inputs organized into dual 9-bit bytes with bytes-oriented output enable and direction control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TD), Test Mode Select (TMS) and Test Clock (TCK). ; die_packaged_part_name SCAN18245TFMQB; die_bonding_diagram bonding diagram can be found on the second page of the bare die data sheet, September 1993. ; die_bsdl s18245t.bsd scan18245t mda_package; die_ibis s18245t.ibs SCAN18245T-MDA; | die_vhdl model_name_refs, top_sim_names; | die_pads_vhdl_map entity_ref bsdl_package_def ; | |------------------------------------------------------------------------------- | geometrical properties |------------------------------------------------------------------------------- die_size 4260 4260; die_size_tolerance 25.0; die_thickness 14mil; die_thickness_tolerance 1.0mil; | |------------------------------------------------------------------------------- | material properties |------------------------------------------------------------------------------- die_substrate_material Si; die_pad_material "Al 99.7% Cu 0.3%"; die_passivation_material "silicon oxynitride" 1.2; die_backside_finish polished; | data sheet specifies "no backside | coating" but does not specify polished | or lapped. We are guessing here | |------------------------------------------------------------------------------- | electrical connection |------------------------------------------------------------------------------- die_substrate_connection optional VCC_supply; |------------------------------------------------------------------------------- | thermal properties of die |------------------------------------------------------------------------------- die_junction_temperature -55 +125; die_power_max 1 uW Not stated in the data sheet; die_power_nom .75uW Not stated in the data sheet.; die_quiescent_current 930uA; die_load_factor 0.25; die_power_capacitance 41pF; | |------------------------------------------------------------------------------- | conditions |------------------------------------------------------------------------------- die_conditions_process maximum temperature 460 degree celsius dwell time (400C rise to 400C fall) 5 minutes; die_conditions_sealing maximum temperature 450 degree Celsius dwell time (at maximum temperature) 8 minutes; die_conditions_storage temperature(degree celsius) -65 to +150, ESD sensitivity class 3; | | pads | die_pads 56 | | pad pad pad center rot pad electrical pad swap | id geometry X Y mir type model name codes | -- ----------- ------- ------- --- -------------- ------------ ----- ----- | 1 3_8milsquare -2025.1 1582.4 0 signal_digital cmos_io_pad B1[4] 1 4 4, 2 3_8milwide -2025.1 1242.4 0 supply_power VCC_supply VCC 0 5 0, 3 3_8milsquare -2025.1 915.7 0 signal_digital cmos_io_pad B1[5] 1 4 5, 4 3_8milsquare -2025.1 698.0 0 signal_digital cmos_io_pad B1[6] 1 4 6, 5 3_8milsquare -2024.9 494.3 0 supply_ground GND_supply GND 0 6 0, 6 3_8milsquare -2025.1 256.3 0 signal_digital cmos_io_pad B1[7] 1 4 7, 7 3_8milsquare -2025.1 87.9 0 signal_digital cmos_io_pad B1[8] 1 4 8, 8 3_8milsquare -2025.1 -87.1 0 signal_digital cmos_io_pad B2[0] 2 3 9, 9 3_8milsquare -2025.1 -255.5 0 signal_digital cmos_io_pad B2[1] 2 3 1, 10 3_8milsquare -2024.9 -493.5 0 supply_ground GND_supply GND 0 6 0, 11 3_8milsquare -2025.1 -697.2 0 signal_digital cmos_io_pad B2[2] 2 3 2, 12 3_8milsquare -2025.1 -914.9 0 signal_digital cmos_io_pad B2[3] 2 3 3, 13 3_8milwide -2025.1 -1241.6 0 supply_power VCC_supply VCC 0 5 0, 14 3_8milsquare -2025.1 -1581.7 0 signal_digital cmos_io_pad B2[4] 2 3 4, 15 3_8milsquare -1891.5 -1976.4 0 signal_digital cmos_io_pad B2[5] 2 3 5, 16 3_8milsquare -1618.7 -1976.4 0 supply_ground GND_supply GND 0 6 0, 17 3_8milsquare -1361.2 -1976.4 0 signal_digital cmos_io_pad B2[6] 2 3 6, 18 3_8milsquare -1040.9 -1976.4 0 signal_digital cmos_io_pad B2[7] 2 3 7, 19 3_8milsquare -774.7 -1976.4 0 signal_digital cmos_input_pad DIR2 2 2 0, 20 3_8milsquare -506.5 -1976.4 0 signal_digital cmos_io_pad B2[8] 2 3 8, 21 3_8milsquare -217.9 -1976.4 0 signal_digital cmos_output_pad TDO, 22 3_8milsquare 140.7 -1976.4 0 signal_digital cmos_test_pad TCK, 23 3_8milsquare 506.5 -1976.4 0 signal_digital cmos_io_pad A2[8] 2 3 8, 24 3_8milsquare 774.7 -1976.4 0 signal_digital cmos_input_pad G2* 2 1 0, 25 3_8milsquare 1040.9 -1976.4 0 signal_digital cmos_io_pad A2[7] 2 3 7, 26 3_8milsquare 1361.2 -1976.4 0 signal_digital cmos_io_pad A2[6] 2 3 6, 27 3_8milsquare 1618.7 -1976.4 0 supply_ground GND_supply GND 0 6 0, 28 3_8milsquare 1891.5 -1976.4 0 signal_digital cmos_io_pad A2[5] 2 3 5, 29 3_8milsquare 2025.1 -1581.7 0 signal_digital cmos_io_pad A2[4] 2 3 4, 30 3_8milwide 2025.1 -1241.2 0 signal_power VCC_supply VCC 0 5 0, 31 3_8milsquare 2025.1 -914.9 0 signal_digital cmos_io_pad A2[3] 2 3 3, 32 3_8milsquare 2025.1 -696.0 0 signal_digital cmos_io_pad A2[2] 2 3 2, 33 3_8milsquare 2025.1 -493.5 0 supply_ground GND_supply GND 0 6 0, 34 3_8milsquare 2025.1 -255.5 0 signal_digital cmos_io_pad A2[1] 2 3 1, 35 3_8milsquare 2025.1 -87.1 0 signal_digital cmos_io_pad A2[0] 2 3 9, 36 3_8milsquare 2025.1 87.9 0 signal_digital cmos_io_pad A1[8] 1 4 8, 37 3_8milsquare 2025.1 256.3 0 signal_digital cmos_io_pad A1[7] 1 4 7, 38 3_8milsquare 2024.9 494.3 0 supply_ground GND_supply GND 0 6 0, 39 3_8milsquare 2025.1 696.7 0 signal_digital cmos_io_pad A1[6] 1 4 6, 40 3_8milsquare 2025.1 915.7 0 signal_digital cmos_io_pad A1[5] 1 4 5, 41 3_8milwide 2025.1 1242.1 0 signal_power VCC_supply VCC 0 5 0, 42 3_8milsquare 2025.1 1582.4 0 signal_digital cmos_io_pad A1[4] 1 4 4, 43 3_8milsquare 1891.5 1976.4 0 signal_digital cmos_io_pad A1[3] 1 4 3, 44 3_8milsquare 1618.7 1976.4 0 supply_ground GND_supply GND 0 6 0, 45 3_8milsquare 1361.2 1976.4 0 signal_digital cmos_io_pad A1[2] 1 4 2, 46 3_8milsquare 1040.9 1976.4 0 signal_digital cmos_io_pad A1[1] 1 4 1, 47 3_8milsquare 774.7 1976.4 0 signal_digital cmos_input_pad G1* 1 1 0, 48 3_8milsquare 506.5 1976.4 0 signal_digital cmos_io_pad A1[0] 1 4 9, 49 3_8milsquare 140.7 1976.4 0 signal_digital cmos_test_pad TDI, 50 3_8milsquare -217.9 1976.4 0 signal_digital cmos_test_pad TMS, 51 3_8milsquare -506.5 1976.4 0 signal_digital cmos_io_pad B1[0] 1 4 9, 52 3_8milsquare -774.7 1976.4 0 signal_digital cmos_input_pad DIR1 1 2 0, 53 3_8milsquare -1040.9 1976.4 0 signal_digital cmos_io_pad B1[1] 1 4 1, 54 3_8milsquare -1361.2 1976.4 0 signal_digital cmos_io_pad B1[2] 1 4 2, 55 3_8milsquare -1618.7 1976.4 0 supply_ground GND_supply GND 0 6 0, 56 3_8milsquare -1891.5 1976.4 0 signal_digital cmos_io_pad B1[3] 1 4 3; | |------------------------------------------------------------------------------- | IBIS model definition (note: separate section) |------------------------------------------------------------------------------- | [MODEL] model_type IBIS model_name s18245t.ibs | [IBIS Ver] 1.1 [Comment char] |_char [File name] s18245t.ibs [File Rev] 1.0 [Date] 10/21/93 [Source] [Notes] [Disclaimer] | Many Component definitions are allowed [Component] SCAN18245T-MDA [Manufacturer] National Semiconductor [Package] | variable typ min max R_pkg 0 0 0 L_pkg 0 0 0 C_pkg 0 0 0 [Pin] signal_name model_name R_pin L_pin C_pin | | Note: The pin section of an IBIS model is not used by the DIE format. | The information should still be provided in case the IBIS file | is extracted and used stand-alone. IBIS has not yet addressed | unpackaged die and, as such, has not defined the meaning of the | pin # for bare die. We suggest using the pad_ID defined in the | DIE format. 1 B1[4] TRANSCEIVER 2 VCC POWER 3 B1[5] TRANSCEIVER 4 B1[6] TRANSCEIVER 5 GND GND 6 B1[7] TRANSCEIVER 7 B1[8] TRANSCEIVER 8 B2[0] TRANSCEIVER 9 B2[1] TRANSCEIVER 10 GND GND 11 B2[2] TRANSCEIVER 12 B2[3] TRANSCEIVER 13 VCC POWER 14 B2[4] TRANSCEIVER 15 B2[5] TRANSCEIVER 16 GND GND 17 B2[6] TRANSCEIVER 18 B2[7] TRANSCEIVER 19 DIR2 INPUT1 20 B2[8] TRANSCEIVER 21 TDO OUTPUT1 22 TCK INPUT2 23 A2[8] TRANSCEIVER 24 G2* INPUT1 25 A2[7] TRANSCEIVER 26 A2[6] TRANSCEIVER 27 GND GND 28 A2[5] TRANSCEIVER 29 A2[4] TRANSCEIVER 30 VCC POWER 31 A2[3] TRANSCEIVER 32 A2[2] TRANSCEIVER 33 GND GND 34 A2[1] TRANSCEIVER 35 A2[0] TRANSCEIVER 36 A1[8] TRANSCEIVER 37 A1[7] TRANSCEIVER 38 GND GND 39 A1[6] TRANSCEIVER 40 A1[5] TRANSCEIVER 41 VCC POWER 42 A1[4] TRANSCEIVER 43 A1[3] TRANSCEIVER 44 GND GND 45 A1[2] TRANSCEIVER 46 A1[1] TRANSCEIVER 47 G1* INPUT1 48 A1[0] TRANSCEIVER 49 TDI INPUT2 50 TMS INPUT2 51 B1[0] TRANSCEIVER 52 DIR1 INPUT1 53 B1[1] TRANSCEIVER 54 B1[2] TRANSCEIVER 55 GND GND 56 B1[3] TRANSCEIVER | |------------------------------------------------------------------------------| | IMPORTANT NOTE: | | These models are what are directly referenced in the DIE format. Note that | | the models below are not complete. They are missing the key pulldown, | | pullup, clamp and ramp specifications. | |------------------------------------------------------------------------------| | | Many Model definitions are allowed [Model] TRANSCEIVER Model_type 3-state Polarity Non-Inverting Enable Active-High | Signals A1[0-8], A2[0-8], B1[0-8], B2[0-8] Vinl = 0.8V Vinh = 2.0V | variable typ min max C_comp 12.0pF NA NA | variable typ min max [Voltage range] 5.0V 4.5V 5.5V | [Pulldown] | Voltage I(typ) I(min) I(max) | -5.0V -40.0m -34.0m -45.0m -4.0V -39.0m -33.0m -43.0m | Example format only 0.0V 0.0m 0.0m 0.0m | Data values are nonsense 5.0V 40.0m 34.0m 45.0m 10.0V 45.0m 40.0m 49.0m | [Pullup] | | Voltage I(typ) I(min) I(max) | -5.0V 32.0m 30.0m 35.0m -4.0V 31.0m 29.0m 33.0m | Example format only 0.0V 0.0m 0.0m 0.0m | Data values are nonsense 5.0V -32.0m -30.0m -35.0m 10.0V -38.0m -35.0m -40.0m | [GND_clamp] | | Voltage I(typ) I(min) I(max) | -5.0V -3900.0m -3800.0m -4000.0m -0.7V -80.0m -75.0m -85.0m | Example format only -0.6V -22.0m -20.0m -25.0m | Data values are nonsense -0.5V -2.4m -2.0m -2.9m -0.4V 0.0m 0.0m 0.0m 5.0V 0.0m 0.0m 0.0m | [POWER_clamp] | | Voltage I(typ) I(min) I(max) | -5.0V 4450.0m NA NA -0.7V 95.0m NA NA | Example format only -0.6V 23.0m NA NA | Data values are nonsense -0.5V 2.4m NA NA -0.4V 0.0m NA NA 0.0V 0.0m NA NA [Ramp] | variable typ min max dV/dt_r 4.2/1.8n 3.5/2.5n 5.0/1.1n | Example format only dV/dt_f 2.5/1.5n 2.0/2.3n 3.0/0.8n | Nonsense data |------------------------------------------------------------------------------| [Model] INPUT1 Model_type input Polarity Non-Inverting Enable Active-Low | Signals G1*, G2*, DIR1, DIR2 Vinl = 0.8V Vinh = 2.0V | variable typ min max C_comp 4.0pF NA NA | variable typ min max [Voltage range] 5.0V 4.5V 5.5V [Pulldown] | Voltage I(typ) I(min) I(max) | -5.0V -40.0m -34.0m -45.0m -4.0V -39.0m -33.0m -43.0m | Example format only 0.0V 0.0m 0.0m 0.0m | Data values are nonsense 5.0V 40.0m 34.0m 45.0m 10.0V 45.0m 40.0m 49.0m | [Pullup] | | Voltage I(typ) I(min) I(max) | -5.0V 32.0m 30.0m 35.0m -4.0V 31.0m 29.0m 33.0m | Example format only 0.0V 0.0m 0.0m 0.0m | Data values are nonsense 5.0V -32.0m -30.0m -35.0m 10.0V -38.0m -35.0m -40.0m | [GND_clamp] | | Voltage I(typ) I(min) I(max) | -5.0V -3900.0m -3800.0m -4000.0m -0.7V -80.0m -75.0m -85.0m | Example format only -0.6V -22.0m -20.0m -25.0m | Data values are nonsense -0.5V -2.4m -2.0m -2.9m -0.4V 0.0m 0.0m 0.0m 5.0V 0.0m 0.0m 0.0m | [POWER_clamp] | | Voltage I(typ) I(min) I(max) | -5.0V 4450.0m NA NA -0.7V 95.0m NA NA | Example format only -0.6V 23.0m NA NA | Data values are nonsense -0.5V 2.4m NA NA -0.4V 0.0m NA NA 0.0V 0.0m NA NA [Ramp] | variable typ min max dV/dt_r 4.2/1.8n 3.5/2.5n 5.0/1.1n | Example format only dV/dt_f 2.5/1.5n 2.0/2.3n 3.0/0.8n | Nonsense data |------------------------------------------------------------------------------| [Model] INPUT2 Model_type input Polarity Non-Inverting Enable Active-Low | Signals TDI, TMS, TCK Vinl = 0.8V Vinh = 2.0V | variable typ min max C_comp 4.0pF NA NA |------------------------------------------------------------------------------| | variable typ min max [Voltage range] 5.0V 4.5V 5.5V [Pulldown] | Voltage I(typ) I(min) I(max) | -5.0V -40.0m -34.0m -45.0m -4.0V -39.0m -33.0m -43.0m | Example format only 0.0V 0.0m 0.0m 0.0m | Data values are nonsense 5.0V 40.0m 34.0m 45.0m 10.0V 45.0m 40.0m 49.0m | [Pullup] | | Voltage I(typ) I(min) I(max) | -5.0V 32.0m 30.0m 35.0m -4.0V 31.0m 29.0m 33.0m | Example format only 0.0V 0.0m 0.0m 0.0m | Data values are nonsense 5.0V -32.0m -30.0m -35.0m 10.0V -38.0m -35.0m -40.0m | [GND_clamp] | | Voltage I(typ) I(min) I(max) | -5.0V -3900.0m -3800.0m -4000.0m -0.7V -80.0m -75.0m -85.0m | Example format only -0.6V -22.0m -20.0m -25.0m | Data values are nonsense -0.5V -2.4m -2.0m -2.9m -0.4V 0.0m 0.0m 0.0m 5.0V 0.0m 0.0m 0.0m | [POWER_clamp] | | Voltage I(typ) I(min) I(max) | -5.0V 4450.0m NA NA -0.7V 95.0m NA NA | Example format only -0.6V 23.0m NA NA | Data values are nonsense -0.5V 2.4m NA NA -0.4V 0.0m NA NA 0.0V 0.0m NA NA [Ramp] | variable typ min max dV/dt_r 4.2/1.8n 3.5/2.5n 5.0/1.1n | Example format only dV/dt_f 2.5/1.5n 2.0/2.3n 3.0/0.8n | Nonsense data |------------------------------------------------------------------------------| | [Model] OUTPUT1 Model_type output Polarity Inverting Enable Active-High | Signals TDO |------------------------------------------------------------------------------| | variable typ min max [Voltage range] 5.0V 4.5V 5.5V [Pulldown] | Voltage I(typ) I(min) I(max) | -5.0V -40.0m -34.0m -45.0m -4.0V -39.0m -33.0m -43.0m | Example format only 0.0V 0.0m 0.0m 0.0m | Data values are nonsense 5.0V 40.0m 34.0m 45.0m 10.0V 45.0m 40.0m 49.0m | [Pullup] | | Voltage I(typ) I(min) I(max) | -5.0V 32.0m 30.0m 35.0m -4.0V 31.0m 29.0m 33.0m | Example format only 0.0V 0.0m 0.0m 0.0m | Data values are nonsense 5.0V -32.0m -30.0m -35.0m 10.0V -38.0m -35.0m -40.0m | [GND_clamp] | | Voltage I(typ) I(min) I(max) | -5.0V -3900.0m -3800.0m -4000.0m -0.7V -80.0m -75.0m -85.0m | Example format only -0.6V -22.0m -20.0m -25.0m | Data values are nonsense -0.5V -2.4m -2.0m -2.9m -0.4V 0.0m 0.0m 0.0m 5.0V 0.0m 0.0m 0.0m | [POWER_clamp] | | Voltage I(typ) I(min) I(max) | -5.0V 4450.0m NA NA -0.7V 95.0m NA NA | Example format only -0.6V 23.0m NA NA | Data values are nonsense -0.5V 2.4m NA NA -0.4V 0.0m NA NA 0.0V 0.0m NA NA [Ramp] | variable typ min max dV/dt_r 4.2/1.8n 3.5/2.5n 5.0/1.1n | Example format only dV/dt_f 2.5/1.5n 2.0/2.3n 3.0/0.8n | Nonsense data |------------------------------------------------------------------------------| | [END] | of IBIS model [MODEL_END] | end of IBIS model section [MODEL] model_type BSDL model_name s18245t.bsd ------------------------------------------------------------------------------- -- -- Copyright National Semiconductor 1992 and Logic Modeling Corporation 1993 -- -- -- National Semiconductor Corporation nor Logic Modeling Corporation makes any -- -- warranty for the use of their products and assumes no responsibility for any -- -- errors which may appear in this file nor does it make a commitment to update -- -- the information contained herein. -- ------------------------------------------------------------------------------- entity scan18245t is generic (PHYSICAL_PIN_MAP : string := "MDA_PACKAGE"); port (G1_NEG:in bit; A1:inout bit_vector(0 to 8); A2:inout bit_vector(0 to 8); G2_NEG:in bit; B1:inout bit_vector(0 to 8); B2:inout bit_vector(0 to 8); GND:linkage bit_vector(0 to 7); VCC:linkage bit_vector(0 to 3); DIR1:in bit; DIR2:in bit; TDO:out bit; TMS, TDI, TCK:in bit); use STD_1149_1_1990.all; -- Get Std 1149.1-1990 attributes and definitions attribute PIN_MAP of scan18245t : entity is PHYSICAL_PIN_MAP; constant SSOP_PACKAGE:PIN_MAP_STRING:="G1_NEG:54, G2_NEG:31," & "B1:(2,4,5,7,8,10,11,13,14), B2:(15,16,18,19,21,22,24,25,27)," & "A1:(55,53,52,50,49,47,46,44,43), A2:(42,41,39,38,36,35,33,32,30)," & "GND:(6,12,17,23,34,40,45,51)," & "VCC:(9,20,37,48)," & "DIR1:3, DIR2:26, TDO:28, TMS:1, TCK:29, TDI:56"; -- bare die pad mapping, numbers are pad_ids from die_pads setting constant MDA_PACKAGE:PIN_MAP_STRING:="G1_NEG:47, G2_NEG:24," & "B1:(51,53,54,56,1,3,4,6,7), B2:(8,9,11,12,14,15,17,18,20)," & "A1:(48,46,45,43,42,40,39,37,36), A2:(35,34,32,31,29,28,26,25,23)," & "GND:(5,10,16,27,33,38,44,55)," & "VCC:(2,13,30,41)," & "DIR1:52, DIR2:19, TDO:21, TMS:50, TCK:22, TDI:49"; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (25.0e6, BOTH); attribute INSTRUCTION_LENGTH of scan18245t : entity is 8; attribute INSTRUCTION_OPCODE of scan18245t : entity is "BYPASS (11111111)," & "EXTEST (00000000)," & "SAMPLE (10000001)," & "HIGHZ (00000011)," & "CLAMP (10000010)"; attribute INSTRUCTION_CAPTURE of scan18245t : entity is "00111101"; attribute INSTRUCTION_DISABLE of scan18245t : entity is "HIGHZ"; attribute REGISTER_ACCESS of scan18245t : entity is "BYPASS (HIGHZ,CLAMP)"; -- HIGHZ and CLAMP attribute BOUNDARY_CELLS of scan18245t : entity is "BC_1, BC_4"; attribute BOUNDARY_LENGTH of scan18245t : entity is 80; attribute BOUNDARY_REGISTER of scan18245t : entity is -- num cell port function safe [ccell disval rslt] "0 (BC_1, A2(8), output3, X, 73, 0, Z)," & "1 (BC_1, A2(7), output3, X, 73, 0, Z)," & "2 (BC_1, A2(6), output3, X, 73, 0, Z)," & "3 (BC_1, A2(5), output3, X, 73, 0, Z)," & "4 (BC_1, A2(4), output3, X, 73, 0, Z)," & "5 (BC_1, A2(3), output3, X, 73, 0, Z)," & "6 (BC_1, A2(2), output3, X, 73, 0, Z)," & "7 (BC_1, A2(1), output3, X, 73, 0, Z)," & "8 (BC_1, A2(0), output3, X, 73, 0, Z)," & "9 (BC_1, A1(8), output3, X, 77, 0, Z)," & "10 (BC_1, A1(7), output3, X, 77, 0, Z)," & "11 (BC_1, A1(6), output3, X, 77, 0, Z)," & "12 (BC_1, A1(5), output3, X, 77, 0, Z)," & "13 (BC_1, A1(4), output3, X, 77, 0, Z)," & "14 (BC_1, A1(3), output3, X, 77, 0, Z)," & "15 (BC_1, A1(2), output3, X, 77, 0, Z)," & "16 (BC_1, A1(1), output3, X, 77, 0, Z)," & "17 (BC_1, A1(0), output3, X, 77, 0, Z)," & "18 (BC_4, B2(8), input, X)," & "19 (BC_4, B2(7), input, X)," & "20 (BC_4, B2(6), input, X)," & "21 (BC_4, B2(5), input, X)," & "22 (BC_4, B2(4), input, X)," & "23 (BC_4, B2(3), input, X)," & "24 (BC_4, B2(2), input, X)," & "25 (BC_4, B2(1), input, X)," & "26 (BC_4, B2(0), input, X)," & "27 (BC_4, B1(8), input, X)," & "28 (BC_4, B1(7), input, X)," & "29 (BC_4, B1(6), input, X)," & "30 (BC_4, B1(5), input, X)," & "31 (BC_4, B1(4), input, X)," & "32 (BC_4, B1(3), input, X)," & "33 (BC_4, B1(2), input, X)," & "34 (BC_4, B1(1), input, X)," & "35 (BC_4, B1(0), input, X)," & "36 (BC_1, B2(8), output3, X, 72, 0, Z)," & "37 (BC_1, B2(7), output3, X, 72, 0, Z)," & "38 (BC_1, B2(6), output3, X, 72, 0, Z)," & "39 (BC_1, B2(5), output3, X, 72, 0, Z)," & "40 (BC_1, B2(4), output3, X, 72, 0, Z)," & "41 (BC_1, B2(3), output3, X, 72, 0, Z)," & "42 (BC_1, B2(2), output3, X, 72, 0, Z)," & "43 (BC_1, B2(1), output3, X, 72, 0, Z)," & "44 (BC_1, B2(0), output3, X, 72, 0, Z)," & "45 (BC_1, B1(8), output3, X, 76, 0, Z)," & "46 (BC_1, B1(7), output3, X, 76, 0, Z)," & "47 (BC_1, B1(6), output3, X, 76, 0, Z)," & "48 (BC_1, B1(5), output3, X, 76, 0, Z)," & "49 (BC_1, B1(4), output3, X, 76, 0, Z)," & "50 (BC_1, B1(3), output3, X, 76, 0, Z)," & "51 (BC_1, B1(2), output3, X, 76, 0, Z)," & "52 (BC_1, B1(1), output3, X, 76, 0, Z)," & "53 (BC_1, B1(0), output3, X, 76, 0, Z)," & "54 (BC_4, A2(8), input, X)," & "55 (BC_4, A2(7), input, X)," & "56 (BC_4, A2(6), input, X)," & "57 (BC_4, A2(5), input, X)," & "58 (BC_4, A2(4), input, X)," & "59 (BC_4, A2(3), input, X)," & "60 (BC_4, A2(2), input, X)," & "61 (BC_4, A2(1), input, X)," & "62 (BC_4, A2(0), input, X)," & "63 (BC_4, A1(8), input, X)," & "64 (BC_4, A1(7), input, X)," & "65 (BC_4, A1(6), input, X)," & "66 (BC_4, A1(5), input, X)," & "67 (BC_4, A1(4), input, X)," & "68 (BC_4, A1(3), input, X)," & "69 (BC_4, A1(2), input, X)," & "70 (BC_4, A1(1), input, X)," & "71 (BC_4, A1(0), input, X)," & "72 (BC_1, *, control, 0)," & "73 (BC_1, *, control, 0)," & "74 (BC_4, G2_NEG, input, X)," & "75 (BC_4, DIR2, input, X)," & "76 (BC_1, *, control, 0)," & "77 (BC_1, *, control, 0)," & "78 (BC_4, G1_NEG, input, X)," & "79 (BC_4, DIR1, input, X)"; end scan18245t; | end of BSDL model [MODEL_END] | end of BSDL model section |------------------------------------------------------------------------------- | Micron Semiconductor S01A 128Kx8 SRAM Bare Die | |------------------------------------------------------------------------------- | pad_Geometry definition sections |------------------------------------------------------------------------------- | [pad_geom] pad_geom_name 4_9milsquare; pad_geom_shape rectangle 4.9mil 4.9mil; | |------------------------------------------------------------------------------- | pad digital signal definition sections |------------------------------------------------------------------------------- | [pad_digital] pad_digital_name minput_pad; pad_digital_circuit cmos input; | The digital circuit info was not provided but the data sheet did state TTL | compatible pads, so we guessed here: pad_digital_threshold 5.5V 2.0V 3.7uA 0.8V -385.0uA; | pad_digital_ibis_model ???; | [pad_digital] pad_digital_name mtrisate_pad; pad_digital_circuit cmos input tristate; | The digital circuit info was not provided but the data sheet did state TTL | compatible pads, so we guessed here: pad_digital_threshold 5.5V 2.0V 1.0uA 0.8V 1.0uA; pad_digital_pull_down 4.5V 48mA 0.55V, 5.5V 48mA 0.55V; pad_digital_pull_up 4.5V -24mA 2.4V, 5.5V -27mA 2.4V; | pad_digital_ibis_model ???; | |------------------------------------------------------------------------------- | power supply pad definition sections |------------------------------------------------------------------------------- | [pad_supply] pad_supply_name mVCC_supply; pad_supply_voltage fixed 5.0V 4.5V 5.5V; pad_supply_current_max 70mA; | [pad_supply] pad_supply_name mGND_supply; pad_supply_voltage fixed 0.0V 0.0V 0.0V; pad_supply_current_max 70mA; | |------------------------------------------------------------------------------- | die definition sections |------------------------------------------------------------------------------- | [die] |------------------------------------------------------------------------------- | administration information |------------------------------------------------------------------------------- die_type bare; die_name MT5C1008S01A; die_manufacturer Micron Semiconductor, Inc; die_mask_version 81C; | note: this is the passivation layer mask version. The other mask layer | versions which would indicate a die shrink are coded in the die_name. | The current die mask version is S01A. | die_section_version 1.1 29/10/92; die_source Information is taken from Micron Semiconductor, Inc. S01A SRAM DIE draft data sheet (rev 1093); | |------------------------------------------------------------------------------- | design information |------------------------------------------------------------------------------- die_technology CMOS; die_description The Micron SRAM family employs high-speed, low-power CMOS designs using a four-transistor memory cell. Micron SRAMs are fabricated using double-layer metal, double-layer polysilicon technology. Micron SRAMs are manufactured and quality controlled in the USA at our Boise, Idaho facility. die_packaged_part_name MT5C1008; die_bonding_diagram bonding diagram can be found on the page 1-4 of the bare die data sheet, REV. 10/93. Caution, the X coordinate of the chip is the vertical dimension of the bonding diagram; | |------------------------------------------------------------------------------- | geometrical properties |------------------------------------------------------------------------------- die_size 13818 6121; | die_size_tolerance die_thickness 18.5mil; die_thickness_tolerance 0.5mil; | |------------------------------------------------------------------------------- | material properties |------------------------------------------------------------------------------- die_substrate_material Si; die_pad_material "Al 98.5% Si 1.0% Cu 0.5%" 9.0; die_passivation_material "silicon nitride" 4.8, "phosphorous doped oxide" 5.8; die_backside_finish polished; | data sheet specifies no backside | coating but does not specify polished | or lapped. | |------------------------------------------------------------------------------- | electrical connection |------------------------------------------------------------------------------- die_substrate_connection isolated; |------------------------------------------------------------------------------- | thermal properties of die |------------------------------------------------------------------------------- die_junction_temperature 0 70; die_power_max 350mW; | die_power_nom not stated in the data sheet. | die_quiescent_current | die_load_factor | die_power_capacitance | |------------------------------------------------------------------------------- | conditions |------------------------------------------------------------------------------- | die_conditions_process | die_conditions_sealing die_conditions_storage filtered nitrogen atmosphere, humidity from 20% to 40%, ESD-protected; | | pads | die_pads 56 | | pad pad pad center rot pad electrical pad swap | id geometry X Y mir type model name codes | -- -------- ----- ----- --- -------------- ----------- ---- ----- | 1 4_9milsquare -6693 2845 0 signal_digital minput_pad A13 1 0 0, 2 4_9milsquare -6693 2591 0 no_connect, 3 4_9milsquare -6693 2235 0 no_connect, 4 4_9milsquare -6693 1905 0 no_connect, 5 4_9milsquare -6693 1550 0 signal_digital minput_pad _WE 0 0 0, 6 4_9milsquare -6693 1219 0 signal_digital minput_pad CE2 0 0 0, 7 4_9milsquare -6693 864 0 signal_digital minput_pad A15 1 0 0, 8 4_9milsquare -6693 559 0 supply_power mVCC_supply VCC 0 5 0, 9 4_9milsquare -6693 356 0 no_connect, 10 4_9milsquare -6693 102 0 supply_power mVCC_supply VCC 0 5 0, 11 4_9milsquare -6693 -101 0 supply_power mVCC_supply VCC 0 5 0, 12 4_9milsquare -6693 -406 0 no_connect, 13 4_9milsquare -6693 -863 0 signal_digital minput_pad A16 1 0 0, 14 4_9milsquare -6693 -1219 0 signal_digital minput_pad A14 1 0 0, 15 4_9milsquare -6693 -1549 0 signal_digital minput_pad A12 1 0 0, 16 4_9milsquare -6693 -1905 0 no_connect, 17 4_9milsquare -6693 -2235 0 no_connect, 18 4_9milsquare -6693 -2591 0 no_connect, 19 4_9milsquare -6693 -2845 0 signal_digital minput_pad A7 1 0 0, 20 4_9milsquare -6363 -2845 0 signal_digital minput_pad A6 1 0 0, 21 4_9milsquare -6363 -2845 0 signal_digital minput_pad A5 1 0 0, 22 4_9milsquare -1512 -2845 0 signal_digital minput_pad A4 1 0 0, 23 4_9milsquare 1536 -2845 0 signal_digital minput_pad A3 1 0 0, 24 4_9milsquare 2806 -2845 0 signal_digital minput_pad A2 1 0 0, 25 4_9milsquare 6388 -2845 0 signal_digital minput_pad A1 1 0 0, 26 4_9milsquare 6693 -2845 0 signal_digital minput_pad A0 1 0 0, 27 4_9milsquare 6693 -2591 0 no_connect, 28 4_9milsquare 6693 -2235 0 no_connect, 29 4_9milsquare 6693 -1905 0 no_connect, 30 4_9milsquare 6693 -1549 0 signal_digital mtristate_pad DQ1 1 1 0, 31 4_9milsquare 6693 -1219 0 signal_digital mtristate_pad DQ2 1 1 0, 32 4_9milsquare 6693 -863 0 signal_digital mtristate_pad DQ3 1 1 0, 33 4_9milsquare 6693 -533 0 supply_ground mGND_supply VSS 0 6 0, 34 4_9milsquare 6693 -330 0 supply_ground mGND_supply VSS 0 6 0, 35 4_9milsquare 6693 149 0 supply_ground mGND_supply VSS 0 6 0, 36 4_9milsquare 6693 -47 0 supply_ground mGND_supply VSS 0 6 0, 37 4_9milsquare 6693 534 0 signal_digital mtristate_pad DQ4 1 1 0, 38 4_9milsquare 6693 864 0 signal_digital mtristate_pad DQ5 1 1 0, 39 4_9milsquare 6693 1219 0 signal_digital mtristate_pad DQ6 1 1 0, 40 4_9milsquare 6693 1550 0 signal_digital mtristate_pad DQ7 1 1 0, 41 4_9milsquare 6693 1897 0 no_connect, 42 4_9milsquare 6693 2227 0 no_connect, 43 4_9milsquare 6693 2591 0 no_connect, 44 4_9milsquare 6693 2845 0 signal_digital mtristate_pad DQ8 1 1 0, 45 4_9milsquare 6388 2845 0 signal_digital minput_pad _CE1 0 0 0, 46 4_9milsquare 2806 2845 0 signal_digital minput_pad A10 1 0 0, 47 4_9milsquare 1536 2845 0 signal_digital minput_pad _OE 0 0 0, 48 4_9milsquare -1512 2845 0 signal_digital minput_pad A11 1 0 0, 49 4_9milsquare -2782 2845 0 signal_digital minput_pad A9 1 0 0, 50 4_9milsquare -6363 2845 0 signal_digital minput_pad A8 1 0 0; | | There is no IBIS model for Micron Semiconductor pads yet! | |------------------------------------------------------------------------------- | Intel Corporation X 30836 SX Bare Die | [pad_geom] pad_geom_name 125square; pad_geom_shape rectangle 125 125; | [pad_geom] pad_geom_name 125double; pad_geom_shape rectangle 125 275; pad_geom_bond_sites 2 0 75 0 -75; | |------------------------------------------------------------------------------- | power supply pad definition section |------------------------------------------------------------------------------- | [pad_supply] pad_supply_name iVCC_supply; pad_supply_voltage fixed 5.0V 4.5V 5.5V; | pad_supply_current_max ???; | [pad_supply] pad_supply_name iGND_supply; pad_supply_voltage fixed 0.0V 0.0V 0.0V; | pad_supply_current_max ???; | |------------------------------------------------------------------------------- | die definition section |------------------------------------------------------------------------------- | [pad_digital] | for all input pins except PEREQ, BUSY#, FLT# and ERROR# pad_digital_name iinput1; pad_digital_circuit cmos input; pad_digital_threshold 4.5V 2.0V 15uA 0.8V 15uA, 5.5V 2.0V 15uA 0.8V 15uA; | pad_digital_ibis_model ???; | [pad_digital] | for PEREQ only pad_digital_name iinput2; pad_digital_circuit cmos input; pad_digital_threshold 4.5V 2.0V 200uA 0.8V 200uA, 5.5V 2.0V 200uA 0.8V 200uA; | pad_digital_ibis_model ???; | [pad_digital] | for BUSY#, FLT# and ERROR# only pad_digital_name iinput3; pad_digital_circuit cmos input; pad_digital_threshold 4.5V 2.0V -400uA 0.8V -400uA, 5.5V 2.0V -400uA 0.8V -400uA; | pad_digital_ibis_model ???; [pad_digital] | for A23 - A1 pad_digital_name ioutput1; pad_digital_circuit cmos output; pad_digital_pull_down 4.5V 4mA 0.45V 0.0uA, 5.5v 4mA 0.45V 0.0uA; pad_digital_pull_up 4.5V -1mA 2.4V 0.0uA, 5.5V -1mA 4.15 0.0uA; | pad_digital_ibis_model ???; | [pad_digital] | for BHE#, BLE#, W/R#, D/C#, M/IO#, LOCK#, ADS#, HLDA pad_digital_name ioutput2; pad_digital_circuit cmos output; pad_digital_pull_down 4.5V 5mA 0.45V 0.0uA, 5.5V 5mA 0.45V 0.0uA; pad_digital_pull_up 4.5V -0.9mA 2.4V 0.0uA, 5.5V -0.9mA 4.15 0.0uA; | pad_digital_ibis_model ???; | [pad_digital] | for D15-D0 pad_digital_name iio1; pad_digital_circuit cmos tristate; pad_digital_threshold 5.5V 2.0V 15uA 0.8V 15uA; pad_digital_pull_down 4.5V 4mA 0.45V 0.0uA, 5.5V 4mA 0.45V 0.0uA; pad_digital_pull_up 4.5V -1mA 2.4V 0.0uA, 5.5V -1mA 4.15 0.0uA; | pad_digital_ibis_model ???; | [die] die_type bare; die_name X80386SX; die_manufacturer Intel Corporation; die_mask_version E1; | die_section_version 1.0 02/11/93; die_source Intel Corp X80386sx(e1) data sheet, 16 April 1993. (x80386sxe1r1.pad1) and Intel386SX microprocessor, Nov 1992. (order number 240187-008); | |------------------------------------------------------------------------------- | design information |------------------------------------------------------------------------------- | | die_size_tolerance | die_technology CHMOS IV; die_description The Intel386SX Microprocessor is an entry-level 32-bit CPU with a 16-bit external data and a 24-bit external address bus.; die_packaged_part_name 80386SX; | |------------------------------------------------------------------------------- | geometrical properties |------------------------------------------------------------------------------- die_size 6172.2 6858; die_thickness 17mil; die_thickness_tolerance 1.0mil; | |------------------------------------------------------------------------------- | material properties |------------------------------------------------------------------------------- die_substrate_material Si; die_backside_finish metallized Au; die_passivation_material 2 nitride 0.3 oxynitride 0.6; | |------------------------------------------------------------------------------- | electrical connection |------------------------------------------------------------------------------- die_substrate_connection optional VCC_supply; |------------------------------------------------------------------------------- | thermal properties of die |------------------------------------------------------------------------------- | die_junction_temperature -55 +125; die_power_max 1.5W; die_power_nom 1.0W; die_quiescent_current 200mA; die_power_capacitance 0; | |------------------------------------------------------------------------------- | conditions |------------------------------------------------------------------------------- | die conditions_bonding not specified | die_conditions_process not specified | die_conditions_sealing not specified die_condition_storage temperature(degree celsius) -65 to +150 ; | die_pad 115 | | no swap code is provided since pins cannot be swapped at all. | | pad pad pad center rot pad electrical pad | id geometry X Y mir type model name | -- -------- - - --- ---- ----- ---- | 1 125square -2908 2936 0 signal_digital ioutput1 A[20], 2 125square -2908 2786 0 signal_digital ioutput1 A[19], 3 125square -2908 2637 0 signal_digital ioutput1 A[18], 4 125square -2908 2487 0 signal_digital ioutput1 A[17], 5 125square -2908 2337 0 supply_power iVCC_supply VCCP, 6 125square -2908 2154 0 signal_digital ioutput1 A[16], 7 125square -2908 1986 0 supply_power iVCC_supply VCC, 8 125square -2908 1836 0 supply_ground iGND_supply VSS, 9 125square -2908 1633 0 no_connect, 10 125square -2908 1448 0 no_connect, 11 125square -2908 1280 0 supply_ground iGND_supply VSSP, 12 125square -2908 1130 0 supply_power iVCC_supply VCCP, 13 125square -2908 960 0 no_connect, 14 125square -2908 775 0 no_connect, 15 125square -2908 589 0 signal_digital ioutput1 A[15], 16 125square -2908 404 0 signal_digital ioutput1 A[14], 17 125square -2908 218 0 signal_digital ioutput1 A[13], 18 125double -2908 -23 0 supply_ground iGND_supply VSSP, 19 125square -2908 -249 0 signal_digital ioutput1 A[12], 20 125square -2908 -399 0 no_connect, 21 125square -2908 -549 0 no_connect, 22 125square -2908 -699 0 signal_digital ioutput1 A[11], 23 125square -2908 -848 0 signal_digital ioutput1 A[10], 24 125square -2908 -1001 0 signal_digital ioutput1 A[9], 25 125square -2908 -1151 0 signal_digital ioutput1 A[8], 26 125square -2908 -1300 0 no_connect, 27 125square -2908 -1461 0 no_connect, 28 125square -2908 -1610 0 supply_power iVCC_supply VCCP, 29 125square -2908 -1760 0 signal_digital ioutput1 A[7], 30 125square -2908 -1910 0 signal_digital ioutput1 A[6], 31 125square -2908 -2060 0 signal_digital ioutput1 A[5], 32 125square -2908 -2212 0 signal_digital ioutput1 A[4], 33 125square -2908 -2362 0 signal_digital ioutput1 A[3], 34 125square -2908 -2525 0 signal_digital ioutput1 A[2], 35 125square -2908 -2715 0 no_connect, 36 125square -2908 -2903 0 no_connect, 37 125square -2908 -3073 0 supply_ground iGND_supply VSSP, 38 125square -2720 -3251 0 supply_ground iGND_supply VSSP, 39 125square -2507 -3251 0 supply_ground iGND_supply VSS, 40 125square -2322 -3251 0 supply_power iVCC_supply VCC, 41 125square -2037 -3251 0 no_connect, 42 125square -1852 -3251 0 no_connect, 43 125square -1656 -3251 0 no_connect, 44 125square -1466 -3251 0 supply_power iVCC_supply VCCP, 45 125square -1280 -3251 0 supply_ground iGND_supply VSS, 46 125square -1095 -3251 0 no_connect, 47 125square -904 -3251 0 no_connect, 48 125square -699 -3251 0 signal_digital iinput1 INTR, 49 125double -439 -3251 90 supply_power iVCC_supply VCC, 50 125square -64 -3251 0 signal_digital iinput1 NMI, 51 125square 241 -3251 0 signal_digital iinput2 PEREQ, 52 125square 427 -3251 0 signal_digital iinput3 ERROR#, 53 125square 706 -3251 0 supply_ground iGND_supply VSS, 54 125square 993 -3251 0 signal_digital iinput3 BUSY#, 55 125square 1245 -3251 0 signal_digital iinput1 RESET, 56 125square 1433 -3251 0 supply_power iVCC_supply VCC, 57 125square 1618 -3251 0 no_connect, 58 125square 1803 -3251 0 no_connect, 59 125square 1971 -3251 0 no_connect, 60 125square 2139 -3251 0 no_connect, 61 125square 2327 -3251 0 no_connect, 62 125square 2512 -3251 0 signal_digital iinput3 FLT#, 63 125square 2908 -3124 0 signal_digital ioutput2 LOCK, 64 125square 2908 -2939 0 signal_digital ioutput2 W/R#, 65 125square 2908 -2753 0 signal_digital ioutput2 D/C#, 66 125square 2908 -2568 0 signal_digital ioutput2 M/IO#, 67 125square 2908 -2383 0 supply_ground iGND_supply VSSP, 68 125square 2908 -2197 0 supply_power iVCC_supply VCCP, 69 125square 2327 -2012 0 no_connect, 70 125square 2908 -1826 0 signal_digital ioutput2 BHE#, 71 125square 2908 -1641 0 signal_digital ioutput1 A[1], 72 125square 2908 -1455 0 signal_digital ioutput2 BLE#, 73 125square 2908 -1270 0 signal_digital ioutput2 ADS#, 74 125square 2908 -1013 0 signal_digital iinput1 CLK2, 75 125square 2908 -813 0 supply_ground iGND_supply VSSP, 76 125double 2908 -554 0 supply_ground iGND_supply VSS, 77 125square 2908 -292 0 supply_ground iGND_supply VSS, 78 125double 2908 -33 0 supply_ground iGND_supply VSS, 79 125square 2908 229 0 supply_power iVCC_supply VCC, 80 125double 2908 488 0 supply_power iVCC_supply VCC, 81 125double 2908 823 0 supply_power iVCC_supply VCC, 82 125square 2908 1085 0 no_connect, 83 125square 2908 1270 0 signal_digital iinput1 READY#, 84 125square 2908 1455 0 signal_digital iinput1 NA#, 85 125square 2908 1641 0 no_connect, 86 125double 2908 1900 0 supply_ground iGND_supply VSS, 87 125square 2908 2162 0 signal_digital iinput1 HOLD, 88 125square 2908 2347 0 signal_digital ioutput2 HLDA, 89 125double 2908 2606 0 supply_ground iGND_supply VSSP, 90 125square 2908 2850 0 signal_digital iio1 D[0], 91 125square 2624 3251 0 signal_digital iio1 D[1], 92 125square 2456 3251 0 signal_digital iio1 D[2], 93 125square 2289 3251 0 supply_ground iGND_supply VSSP, 94 125square 2134 3251 0 supply_power iVCC_supply VCCP, 95 125square 1981 3251 0 signal_digital iio1 D[3], 96 125square 1829 3251 0 signal_digital iio1 D[4], 97 125square 1674 3251 0 signal_digital iio1 D[5], 98 125square 1519 3251 0 signal_digital iio1 D[6], 99 125square 1364 3251 0 signal_digital iio1 D[7], 100 125double 1057 3251 270 supply_power iVCC_supply VCC, 101 125square 706 3251 0 signal_digital iio1 D[8], 102 125square 554 3251 0 signal_digital iio1 D[9], 103 125square 399 3251 0 signal_digital iio1 D[10], 104 125square 244 3251 0 signal_digital iio1 D[11], 105 125square 89 3251 0 signal_digital iio1 D[12], 106 125square -64 3251 0 supply_ground iGND_supply VSSP, 107 125square -218 3251 0 supply_power iVCC_supply VCCP, 108 125square -373 3251 0 signal_digital iio1 D[13], 109 125square -528 3251 0 signal_digital iio1 D[14], 110 125square -696 3251 0 signal_digital iio1 D[15], 111 125square -1158 3251 0 signal_digital ioutput1 A[23], 112 125square -1321 3203 0 signal_digital ioutput1 A[22], 113 125double -1577 3167 270 supply_ground iGND_supply VSS, 114 125double -2286 3251 270 supply_power iVCC_supply VCCP, 115 125square -2548 3251 0 signal_digital ioutput1 A[21]; | | There is no IBIS model for this Intel part yet! | [DIE_Block_end]